Poster Session 2 w/ Brief Oral Presentations
(15:45-17:45, Aug. 22, 2017 (Day 2))

Room A (for Brief Oral Presentations)

# Title/Author(s)
2A-1 915 MHz Energy Harvester Design for 2.4 GHz RFID Tag with Harmonic Enhanced Location Detection
Chun-Jung Peng, Sheng-Fan Yang, and Tzuen-Hsi Huan
2A-2 Investigation of Fluctuating Phase Differences of Complex Waves on A Ring with Many Van Der Pol Oscillators
Ryouhei Takano and Masayuki Yamauchi
2A-3 Low Power Design Flow with Static and Statistical Timing Aanalysis
Ko-Chi Kuo and Hsueh-Ta Ko
2A-4 Parallel Connected DC-DC Converter
Muhammad Fakihin Abdullah, Hirokazu Ohtagaki, Takuji Kousaka, Kenta Shinohara, and Hiroyuki Asahara
2A-5 Front-end Amplifier Design for Application of High-Speed Circuit Testing
Jun-Ying Lai and Chien-Nan Kuo
2A-6 Synchronization Phenomena in Coupled Symmetrical Structures of Chaotic Circuit
Katsuki Nakashima, Kazuki Ueta, Yoko Uwate, and Yoshifumi Nishio
2A-7 A simple switchable dual-frequency matching network
Ming-Lin Chuang, Ming-Tien Wu, and Tsan-Chun Chan
2A-8 Passivity-based Control and Energy Function Shaping for Ring Coupled Converter Systems
Rutvika Nandan Manohar and Takashi Hikihara

Room B (for Brief Oral Presentations)

# Title/Author(s)
2B-1 An Embedded Virtual Processor System
Shih-Chieh Hsu, Kuan-Chung Chen, and Chung-Ho Chen
2B-2 Stabilization of Mode in Imbalanced Operation of Matrix Converter by Delayed Feedback Control
Manuel Antonio Sanchez and Takashi Hikihara
2B-3 Novel Two-dimension Sliding Discrete Fourier Transform Algorithm and its Hardware Architecture Design
Wen-Ho Juang, Shin-Chi Lai, Ching-Hsing Luo, and Shuenn-Yuh Lee
2B-4 Equilibrium Point Analysis of a Decentralized Discrete-Time System for Algebraic Connectivity Estimation
Kento Endo, Norikazu Takahashi, and Sang-Gu Lee
2B-5 Approximate Decoding for RBFNN-Based Texture Compression
Lin Yu-Kuan and Kuo Chich-Hung
2B-6 Capacitive Open Detection in 3D ICs with A Built-in Comparator of Offset Cancellation Type
Michiya Kanda, Masaki Hashizume, Hiroyuki Yotsuyanagi, and Shyue-Kung Lu
2B-7 A Low Latency Memory I/O Link Compression Architecture for GPU
Meng-Yang Lu and Chih-Hung Kuo
2B-8 On design for reducing delay variation in design-for-testability circuit for delay fault
Satoshi Hirai, Hiroyuki Yotsuyanagi, and Masaki Hashizume

Room C (for Brief Oral Presentations)

# Title/Author(s)
2C-1 Dynamic Voltage Scaling (DVS) Voltage Regulator with Fast Reference Tracking Ability
Chun-Wei Ho and Le-Ren Chang-Chien
2C-2 Analysis of Synchronization Phenomena with Frustration Networks
Kazuki Ueta, Yoko Uwate, and Yoshifumi Nishio
2C-3 A Single-Inductor-Multiple-Output Boost Converter for Thermoelectric Energy Harvesting With 280mV Cold-start, Maximum Power Point Tracking, And Buck-Boost Converter
Ching-Yen Chiu and Sheng-Yu Peng
2C-4 Investigation of A Special Wave-Motion of Phase Differences between Adjacent Oscillators on A Ring with 8 Van Der Pol Oscillators
Rika Hirano, Ryouhei Takano, and Masayuki Yamauchi
2C-5 A 96% Efficiency Single Inductor Multiple Floating Output (SIMFO) LED Driver with 24-bit Color Resolution
Yu-Quien Liu, Han-Hsiang Huang, and Ke-Horng Chen
2C-6 Five-segment PWL conductance in a Josephson junction
Yuu Miino and Tetsushi Ueta
2C-7 Monitor-based Power Management Scheme for GPGPU
Chao-Kai Yang, Che-Pin Chang, and Lih-Yih Chiou
2C-8 Asynchronous CA spiking neural network and its classification function
Taiki Naka and Hiroyiki Torikai

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